Various types of flat panel displays such as liquid crystal displays (LCDs), plasma display panels (PDPs), electroluminescence display panels, etc., have been developed to replace traditional cathode ray tube (CRT) displays. Such flat panel displays are suitable for devices and applications requiring small dimension, lightweight and low power consumption. For example, LCDs can be operated using large-scale integration (LSI) drivers since LCDs can be driven by a low-voltage power supply and have low power consumption. Accordingly, LCDs have been widely implemented for laptop computers, cellular phones, pocket computers, automobiles, and color televisions, etc. The lightweight, smaller dimension, and lower power consumption features of LCD devices render such display devices suitable for use with, e.g., portable, handheld devices.
FIG. 1 is a schematic diagram that illustrates a conventional display system. The display system (10) comprises a display panel (11) (e.g., LCD) and a plurality of components for driving/controlling the display panel (11) including a source driving IC (12), a gate driving IC (13), a controller having a GRAM (graphic random access memory) (14), and a power generator (15). The controller (14) generates control signals to control the power generator (15), the source driving IC (12) and the gate driving IC (13).
The display panel (11) comprises a plurality of data lines (D1˜Dn) that are connected to the source driving IC (12) and a plurality of gate lines (G1˜Gm) that are connected to the gate driving IC (13). The display panel (11) comprises a plurality of pixels/subpixels that are arrayed in a matrix of rows and columns, wherein the pixels/subpixels in a given row are commonly connected to a gate line and wherein the pixels/subpixels in a given column are commonly connected to a data line. Depending on the application/design, one pixel/subpixel is composed in each interconnection of a gate line and data line.
Assuming the display panel (11) is a TFT-LCD, the display panel (11) would include a thin-film transistor (TFT) board comprising a plurality of pixel/subpixel units arranged in matrix form. As shown in FIG. 1, each pixel/subpixel unit comprises a TFT, a liquid crystal capacitor (Cp), which is connected between a drain electrode of the TFT and a common electrode (VCOM) and a thin-film storage capacitor (Cst), which is connected in parallel with the liquid crystal capacitor (Cp). The storage capacitor (Cst) stores an electric charge so that an image on the display is maintained during a non-selected period. The liquid crystal capacitor (Cp) is formed by a common electrode (VCOM) of a color filter plate, a pixel electrode of the TFT and liquid crystal material therebetween. A source electrode of the TFT is connected to a data line and a gate electrode of the TFT is connected to a gate line. The TFT acts as a switch that applies a source voltage on the data line to the pixel electrode when a gate driver signal VGH on the gate line is applied to the gate of the TFT.
The power generator (15) generates a plurality of reference voltages, including, AVDD (source driver power supply) and GVDD (gamma reference voltage), which are applied to the source driving IC (12), VCOMH (high common electrode voltage) and VCOML (low common electrode voltage), which are applied to the common voltage electrode (VCOM) of the panel (11), and VGH(gate driver turn-on voltage) and VGOFF (gate driver turn-off voltage), which are applied to the gate driving IC (13) to drive selected gate lines.
The controller (14) receives as input a plurality of driving data signals and driving control signals that are output from an image supply source (e.g., a main board of a computer). The driving data signals comprise R, G, B data for forming an image on the display (11). The driving control signals comprise vertical synchronous signals (Vsynch), horizontal synchronous signals (Hsync), a data enable signal (DE) and a clock signal (Clk). The controller (14) outputs to the source driving IC (12) a plurality of display data signals (DDATA), which correspond to R, G, B data, and a source control signals. The controller (14) outputs a gate control signals to control the gate driving IC (13). The controller (14) controls the timing for which data and control signals are output from the source driving IC (12) and gate driving IC (13). For example, in one mode of operation, the controller (14) generates the source and gate control signals such that the gate driving IC (13) transmits a gate driver output signal VGH to each gate line (G1˜Gm) in a consecutive manner and data voltage is selectively applied to each pixel/subpixel in an activated row one by one in order. In another mode of operation, the pixels/subpixels can be charged by sequentially scanning pixels/subpixels in a first column and thereafter scanning pixels/subpixels in a next column.
The gate driving IC (13) comprises a plurality of gate drivers that each drive a corresponding gate line G1˜Gm. The source driving IC (12) comprise a plurality of source driver circuits (12-1˜12-n), or more generally, 12(i), which drive corresponding data lines D1˜Dn. FIG. 2 schematically illustrates a conventional source driver circuit (20), which can be implemented in the system (10) of FIG. 1 for driving the data lines of the display panel (11). In general, as depicted in FIG. 2, the source driver circuit (20) comprises a source driver (12-i) that drives a corresponding data line (Di), and a grayscale voltage generator (23). The source driver circuit (20) of FIG. 2 illustrates a conventional architecture of the source driver IC (12) of FIG. 1, wherein there is one source driver (12-i) for each data line (or RGB channel). The grayscale generator (23) can be implemented in the power generator circuit (15) of FIG. 1. The output of the grayscale generator (23) is commonly applied to each source driver (12-1˜12-n) of the source driver IC (12).
In general, the source driver (12-i) comprises a polarity reverse circuit (21), a latch circuit (22), a gamma decoder (24), and a driving buffer (25). The source driver (12-i) is controlled by a plurality of control signals, including a polarity control signal M, a latch control signal S_Latch, and mode control signals GRAY_ON (gradient mode enable signal) and BIN_ON (binary mode enable signal), each of which will be explained below. Moreover, the source driver (12-i) receives as input grayscale reference voltages that are generated by the grayscale voltage generator (23).
The source driver (12-i) receives as input an n-bit block of display data (DDATA) for R, G or B data from the GRAM (14). The polarity reverse circuit (21) receives the display data block (DDATA) and controls a polarity of the n-bits in response to the polarity control signal M. For example, if the polarity control signal M is logic “0”, the polarity of the display data (DDATA) will remain the same (original display data (positive polarity)). On the other hand, if the polarity control signal M is logic “1”, the polarity of the display data (DDATA) will be reversed (inverted display data (negative polarity)). In the embodiment of FIG. 2, the polarity reverse circuit (21) is implemented using an exclusive-OR (XOR) gate.
The latch circuit (22) latches the n-bit data block output from the polarity reverse circuit (21) in response to a latch control signal S_LATCH. In the embodiment of FIG. 2, the latch circuit (22) is implemented using a clocked n-bit D latch. The latch circuit (22) latches and outputs a latched display data block CD[n-1:0] to the gammna decoder (24). The gray scale voltage generator (23) generates and outputs 2n different grayscale reference voltages (VG[2n-1:01])to the gamma decoder (24). The gamma decoder (24) decodes the n-bit display data block CD[n-1:0] output from the latch circuit (22), and selects and outputs a grayscale voltage to the driving buffer (25). For each pixel (comprising RGB subpixels), the number of possible grayscales (or different colors) that can be generated for each pixel with the n-bit grayscale architecture is 2n(R)2n(G)2n(B)=23n.
The driving buffer (25) comprises a first driver (26), a first driver output switch (S1), and a second driver (27). The first driver (26) buffers and amplifies a grayscale voltage output from the gamma decoder (24) and the second driver (27) buffers and amplifies the MSB (most significant bit), CD[n-1], of the latched display data CD[n-1:0]. The driving buffer (25) generates a source driver output signal Sn for driving a corresponding data line Di, which will vary depending on selected mode of operation, i.e., binary mode (8-color mode) or gradient mode (23n-color mode).
For instance, in gradient mode, a GRAY_ON control signal is enabled (logic “1”) to activate (close) the switch S1, thereby allowing the first driver (26) to output a buffered grayscale voltage. Further, in gradient mode, a BIN_ON control signal (which is applied to the second driver (27)) is disabled (logic “0”) to deactivate (turn off) the second driver (27). On the other hand, in binary mode, the GRAY_ON control signal is disabled (logic “0”) to deactivate (open) the switch S1, thereby preventing the first driver (26) from outputting a buffered grayscale voltage as Sn, and the BIN_ON control signal is enabled (logic “1”) to activate the second driver (27). In binary mode, the second driver (27) will output a source driver output signal Sn of AVDD (power supply voltage for source driver) or AVSS (ground voltage for source driver), depending on the logic level of the most significant bit CD[n-1] of the latched display data CD[n-1:0].
FIG. 3 is a timing diagram illustrating a binary mode of operation of the source driver circuit of FIG. 2. In FIG. 3, it is assumed that the resolution of the RGB data is 6 bits (i.e., n=6) and that latched display data CD[n-1:0] having values 00H (binary 000000), 3FH(binary 111111), 07H(binary 000111) and 19H(binary 011001) are successively output from the latch (22). As shown in FIG. 3, in binary mode, BIN_ON is fixed at logic “1” and GRAY_ON is fixed at logic “O”. As such, the switch S1 is open and the second driver (27) is activated.
As further depicted in FIG. 3, before time T1, the latched display data CD[5:0] of value 00H has a most significant bit CD[5]=logic “0”, which results in a source driver output signal Sn of AVSS (ground for the source driver) being output from the second driver (27). At time T1, a latch control pulse S_LATCH results in a latched display data CD[5:0]=3FH, which has a most significant bit CD[5]=logic “1”. In response, the source driver output signal Sn (output from the second driver (27)) transitions from AVSS to AVDD (the power supply voltage level for the source driver). Then, at time T2, a latch control pulse S_LATCH results in a latched display data CD[5:0]=07H, which has a most significant bit CD[5]=logic “0”. In response, the source driver output signal Sn output from the second driver (27) transitions from AVDD to AVSS. Then, at time T3, a latch control pulse S_LATCH results in a latched display data CD[5:0]=19H, which has a most significant bit CD[5]=logic “0”. In response, the source driver output signal Sn remains at AVSS.
FIG. 4 is a timing diagram illustrating a gradient mode of operation of the source driver circuit of FIG. 2. In FIG. 4, it is assumed that the resolution of the RGB data is 6 bits (i.e., n=6) and that latched display data blocks CD[n-1:0] having values 00H (binary 000000), 3FH (binary 111111), 07H (binary 000111) and 19H (binary 011001) are successively output from the latch (22). As shown in FIG. 4, in binary mode, BIN_ON is fixed at a logic “0” and GRAY_ON is fixed at logic “1”. As such, the second driver (27) is deactivated, the switch S1 is activated (closed) and the first driver (26) buffers and outputs as Sn, the grayscale voltage selected by the decoder (24).
More specifically, as depicted in the exemplary diagram of FIG. 4, before time T1, the latched display data CD[5:0]=00H results in a source driver output signal Sn of value VG[0]. At time T1, a latch control pulse S_LATCH results in a latched display data block CD[5:0]=3FH, which causes Sn to transition from VG[0] to VG[63]. Then, at time T2, a latch control pulse S_LATCH results in a latched display data CD[5:0]=07H, which causes Sn to transition from VG[63] to VG[7]. Then, at time T3, a latch control pulse S_LATCH results in a latched display data CD[5:0]=19H, which causes the source driver output signal Sn to transition from VG[7] to VG[25].
FIG. 5 schematically illustrates a conventional common voltage driver circuit (30), which is implemented in the system (10) of FIG. 1 for driving the common electrode (VCOM) of the display panel (11). In general, the common voltage driver (30) comprises first and second drivers (31) and (32), switches (33) and (34) and capacitors (35) and (36). The first driver (31) buffers and outputs VCOMH (high common voltage). As explained below, a VCOMH voltage generator in the power generating circuit (15) generates VCOMH from AVDD power. The capacitor (35) is connected to the output of the first driver (31) to stabilize the output voltage. The switch (33) is controlled by control signal VCMH_ON to selectively connect the output of the first driver (31) to a VCOM node N and drive VCOM to a high common voltage VCOMH.
The second driver (32) buffers and outputs VCOML (low common voltage). As explained below, a VCOML voltage generator in the power generating circuit (15) generates VCOML from VCL (−VCI) power. The capacitor (36) is connected to the output of the second driver (32) to stabilize the output voltage. The switch (34) is controlled by a control signal VCML_ON to selectively connect the output of the second driver (32) to the VCOM node N and drive VCOM to VCOML.
FIG. 6 is an exemplary timing diagram illustrating a conventional method for driving a common electrode using the circuit of FIG. 5. Referring to FIG. 6, at time T1, the polarity control signal M and control signal VCMH_ON are enabled and the control signal VCML_ON is disabled. As a result, switch (33) is activated and switch (34) is deactivated and VCOM is driven to VCOMH from VCOML by the first driver (31). At time T2, the polarity control signal M and control signal VCMH_ON are disabled and the control signal VCML_ON is enabled. As a result, switch (33) is deactivated and switch (34) is activated and VCOM is driven to VCOML from VCOMH by the second driver (32).
When display systems such as LCD panels are implemented in small hand-held, portable devices, it is important to reduce the power consumption needed to drive such displays so as to preserve battery power. In general, the primary sources of power consumption for driving flat panel displays include source drivers and VCOM drivers. More specifically, with source drivers, the voltages for driving the data lines are typically designed with relatively high levels in order to enhance the driving speed of the display (e.g., quickly charge the liquid crystal capacitor Cp). However, an increased driving voltage increases power consumption of the display in proportion to the voltage rise of the driving voltage. Further, driving the common electrode (which faces the pixel electrodes) is a significant source of power consumption because the polarity of the common voltage is reversed every cycle.
Typically, source and VCOM driving voltages are internal voltages that are generated by voltage generators that generate such driving voltages by boosting voltage/power output from an intermediate reference voltage source. For example, FIG. 7 is a block diagram illustrating a conventional architecture of the power generator (15) in FIG. 1. In general, the power generator (15) generates a plurality of internal reference voltages using an intermediate reference voltage VCI supply source. More specifically, the power generator (15) comprises a first power generator (15-1) that generates AVDD (source driver power supply voltage) by boosting an intermediate input voltage VCI by a predetermined amount α (which is greater than 1). The AVDD voltage is applied to the source driver (12), and is input to other power generators (not shown) to generate GVDD and VCOMH. A second power generator (15-2) receives the reference voltage AVDD as input and generates VGH by boosting AVDD by an amount β. A third power generator (15-3) receives the reference voltage VGH as input and generates VGL=−VGH. A fourth power generator (15-4) receives the intermediate reference voltage VCI as input and generates VCL=−VCI.
One problem associated with the conventional source and VCOM driver circuits is the significant power consumption that occurs due to the use of boosted power to drive the data lines and VCOM. More specifically, by way of example with reference to FIG. 2, the first and second drivers (26) and (27) in the driving buffer (25) use boosted AVDD power to drive the data line, and in FIG. 5, the boosted AVDD power is used for generating VCOMH (high common voltage) and driving the common electrode VCOM of the display panel (11). For AVDD, the power consumption is PAVDD=IAVDD·AVDD=α·IAVDD·VCI and the driving current IAVDD is supplied from the intermediate power supply VCI. Although the current dissipation for driving current IAVDD is derived from VCI power, the actual power consumption based on AVDD power is greater when α1. Accordingly, the boosted power for AVDD and VCOMH for driving the data lines and VCOM effectively results in more power consumption for the same current dissipation IAVDD.